NEW 3D COMPUTER CHIP TO BOOST PROCESSING POWER
The new 3D computer chip which combines two leading edge of nanotechnology could hysterically increase the speed and energy efficiency of a processor.
The presently used chip separates memory (which stores data) and logic circuit (which process data). Data is moved to and fro between both units to carry out operations, but due to the finite number of connection between memory and logic circuit, this has become a major barrier since computers are expected to deal with ever rising amount of data.
This drawback was masked by the observation of Gordon Moore (co-founder of fairchild semiconductor and intel) named after him as Moore’s law, which states that the number of transistor that can fit on a chip doubles every two years.
The new prototype chip, designed by engineers from Stanford University and the Massachusetts Institute of Technology, tackles both problems simultaneously by layering memory and logic circuits on top of each other, rather than side by side. Research shows that it does not only make effective use of space, but also enhances the surface area connection between components. A conventional logic circuit would have a limited number of pins on each edge through which they relay data, by contrast, the researchers were not limited to using edges and were able to densely pack vertical wires running from memory layer to logic layer.
On top of this, the researchers used logic circuits constructed from carbon nano-tube transistors, along with an emerging technology called resistive random-access memory (RRAM), both of which are much more energy-efficient than silicon technologies. This is important because the huge energy needed to run data centers constitutes another major challenge facing technology companies.While both of these new nanotechnologies have inherent advantages over conventional, silicon-based technology, they are also integral to the new chips 3D architecture.
The reason why today’s chip is 2D is because assembling silicon transistors onto a chip requires temperatures of more than 1,800 degrees Fahrenheit (1,000 degrees Celsius), which makes it impossible to layer silicon circuits on top of each other without damaging the bottom layer, unlike the carbon nano-tube and RRAM which are fabricated at temperature cooler than 392 degrees F (200 degrees C), so they can easily be layered on top of silicon without damaging the underlying circuitry.
Stacking many layer on-top each other may lead to heating, but in this case it can be ignored since this technology has increased energy efficiency so little heat is generated.
The chip is highly versatile and particularly well-suited to the kind of data-heavy, deep neural network
approaches that underpin current artificial intelligence technology.
“These structures may be particularly suited for alternative learning-based computational paradigms such as brain-inspired systems and deep neural nets, and the approach presented by the authors is definitely a great first step in that direction”.